Areas of interest include methods, tools, methodologies and development environments.
Track Chair: Ayse Kivilcim Coskun, Boston University, US, Contact Ayse Kivilcim Coskun Topics Modeling and specification methodologies for complex HW-SW systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core So Cs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.In topic A8, there is the opportunity to submit short, 2-page papers that relate to industrial research and practice. anzeigen sie sucht ihn Münster Track Chair: Ian O'Connor, Ecole Centrale de Lyon, FR, Contact Ian O' Connor Topics Application design experiences in industrial or academic projects with high industrial relevance or high environmental impact, targeting high performance or large-scale computing systems with a focus on energy efficiency.Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automatic place and route; interconnect- and performance-driven layout; process technology developments.Parasitic and variation-aware extraction for on-chip interconnect and passives; Macro-modeling, behavioral and reduced order modeling; Modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate.
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Target systems are massively parallel (super) computers, 2D/3D many-core systems, high performance computing clusters, data centers, cloud systems and cyber-physical systems.Topics of interest include, but are not limited to: software architectures for energy-efficient computing, virtualization, energy-efficient memory, processor, or communication architectures including non-volatile memory architectures and their use as storage components in datacenters, heterogeneous computing, resource management techniques including adaptive/learning-based methods, innovative data-center management strategies, big-data management, data centers powered by renewable energy sources, and data centers in smart-grids.Algorithms, techniques and tools for power modeling, estimation and optimization of electronic systems applicable at all levels of the design, including both hardware and software; dynamic power management and leakage currents minimization; design flows and circuit architectures for ultra-low power consumption. Architecture and modeling techniques for No C; Design methodologies and architectures for on-chip interconnection networks: topology, switching, routing and flow control; No C service frameworks for Quality of Service, security and power management; Techniques and methodologies for No C testing; GALS and asynchronous architectures for No Cs; Integration of external interfaces/memory controllers with No Cs; Cache-coherent No Cs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, No C design space exploration frameworks; Programming models for No C-based platforms; design of No Cs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).Architectural and micro-architectural design techniques; memory systems; power and energy efficient architectures; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for reliability, security, timing predictability.Covering all test, design-for-test, reliability and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analog and digital electronics.
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Including also diagnosis, failure mode analysis, debug and post-silicon validation challenges.Modeling, circuit design and design automation flows for future computing including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (TSV modeling and design space exploration).Modeling, circuit design and design automation flows for future data storage including: non-CMOS memory (e.g., MRAM, STT-RAM, Fe RAM, PCRAM, RRAM, Ox RAM, quantum dots etc.); advances in flash memory technology; memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile cache etc.); memory management techniques for emerging memories.Methods, techniques and architectures for counteracting variability of digital circuits and systems due to manufacturing, thermal or aging effects; design and run-time thermal, variability and reliability management of So Cs and multi-core platforms (both at hardware and software level); modeling and optimization approaches for manufacturing and temperature variations and degradation mechanisms in emerging 3D integration and manufacturing technologies.Reconfigurable computing platforms and architectures; heterogeneous platforms (FPGA/GPU/CPU); reconfigurable processors; reconfigurable computing for high performance and data centers; statically and dynamically reconfigurable and reprogrammable systems and components; FPGA architectures and FPGA circuit design; design methods and tools for reconfigurable computing and communication systems.